Documentos Técnicos
Especificações
Brand
NexperiaProduct Type
Shift Register
Mount Type
Surface
Maximum Supply Voltage
6V
Minimum Operating Temperature
-40°C
Maximum Operating Temperature
125°C
Standards/Approvals
RoHS
Detalhes do produto
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
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R$ 561,00
R$ 11,22 Each (In a Tube of 50) (Sem VAT)
50
R$ 561,00
R$ 11,22 Each (In a Tube of 50) (Sem VAT)
Informações de estoque temporariamente indisponíveis.
50
| Quantidade | Preço unitário | Per Tubo |
|---|---|---|
| 50 - 50 | R$ 11,22 | R$ 561,00 |
| 100 - 200 | R$ 10,43 | R$ 521,50 |
| 250 - 450 | R$ 10,34 | R$ 517,00 |
| 500 - 950 | R$ 10,21 | R$ 510,50 |
| 1000+ | R$ 10,13 | R$ 506,50 |
Ideate. Create. Collaborate
JOIN FOR FREE
No hidden fees!
Documentos Técnicos
Especificações
Brand
NexperiaProduct Type
Shift Register
Mount Type
Surface
Maximum Supply Voltage
6V
Minimum Operating Temperature
-40°C
Maximum Operating Temperature
125°C
Standards/Approvals
RoHS
Detalhes do produto
The 74HC4094, 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH.
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JOIN FOR FREE
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